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Coreboot build script fails on Librem 13v1 device
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Found chipset "Intel Broadwell U Premium".
This chipset is marked as untested. If you are using an up-to-date version
of flashrom *and* were (not) able to successfully update your firmware with it,
then please email a report to including a verbose (-V) log.
Thank you!
Enabling flash write... Warning: SPI Configuration Lockdown activated.
Found Programmer flash chip "Opaque flash chip" (8192 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
Reading flash... done.
File ../coreboot-orig.rom is 8388608 bytes
  Flash Region 0 (Flash Descriptor): 00000000 - 00000fff 
  Flash Region 1 (BIOS): 00200000 - 007fffff 
  Flash Region 2 (Intel ME): 00001000 - 001fffff 
  Flash Region 3 (GbE): 00fff000 - 00000fff (unused)
  Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
--2018-07-15 21:53:23--
Resolving (,
Connecting to (||:443... connected.
HTTP request sent, awaiting response... 404 Not Found
2018-07-15 21:53:24 ERROR 404: Not Found.

Changing the build script BDL_UCODE_URL from to from (and changing its sha256 sum to a8b2cc7b62e4cd1e0b077f1b6cfb69c33efb238c430b8005471f19b78d9dd416) makes the build script succeed.

Event Timeline

mladen created this task.Jul 15 2018, 13:04
mladen created this object with edit policy "Restricted Project (Project)".
mladen updated the task description. (Show Details)Jul 15 2018, 13:08**B_2018-03-22_PRD_0B0DD00D**.bin//

actually, you'd want to change the link to use the latest commit hash, not master, otherwise the script will break again next time the microcode is updated. So instead use:**B_2018-03-22_PRD_0B0DD00D**.bin//

unless we want the script to break as a reminder to update the microcode URL

mladen updated the task description. (Show Details)Jul 15 2018, 13:49

Humm.. I thought that repo was meant to contain an archive of all microcodes, I didn't realize he deleted old ones when new ones are out.
I'll update the link and use the commit hash, I prefer that than having the script break constantly.

kakaroto closed this task as Resolved.Jul 16 2018, 12:08
kakaroto claimed this task.

I fixed it by using the old commit hash for the previous microcode. I didn't want to update the microcode since that would mean changing the version (so, changing the config, adding a new tag, rebuilding all, changing coreboot final hashes, changelog, etc..) and I'd like to do it later when I update the FSP for the skylake ones as well, but that one needs testing first and I wanted this fix to be out asap.